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HELP - RFID tag And Manchester coding

 
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Kimowich



Joined: 16 May 2013
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HELP - RFID tag And Manchester coding
PostPosted: Thu May 16, 2013 1:52 pm     Reply with quote

Hi

Using a PIC16f887 and PWC ver 4.084
I have an assignment where I have made a RFID tag sending a manchester encoded signal which i have connected to the analog comparator to get a clean digital signal.

Now the assignment says that i must separate the clock from the data somehow.

And I am completely lost.

I need some pointers in how you can do this.
Gabriel



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PostPosted: Thu May 16, 2013 3:05 pm     Reply with quote

manchester reads in the middle of the signal and not on edges...(transitions)

from what i understand you are the one generating the signal to decode... thus you know the exact signal timing...

you could wait for the initial edge and then trigger a read half a time constant later... and then the next read will be at a full time constant since the first read... efectively reading at the mid point of every bit....

... wikipedia has a nice manchester code article... with graphs..

G.
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CCS PCM 5.078 & CCS PCH 5.093


Last edited by Gabriel on Thu May 16, 2013 3:17 pm; edited 1 time in total
Gabriel



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PostPosted: Thu May 16, 2013 3:07 pm     Reply with quote

also, the clock cycle is 2 times the smallest bit duration....
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FvM



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PostPosted: Thu May 16, 2013 11:41 pm     Reply with quote

If it's a passive RFID (e.g. ISO 14443A), the clock will be usually derived from the carrier.

But generally, it can be extracted from the received signal by a PLL. Depending on the bit rate, an "all-digital" PLL in software might work.
Kimowich



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PostPosted: Fri May 17, 2013 3:42 am     Reply with quote

i think my real problem is that i cant seem to figure out how to get those readings.

As far as i can see on my Scope, the clock is 2 Khz and if i want a middle read.

I know i can use the comparator interrupt to know when it shifts transition.

But how do i set the timer so that it will take the measurments correct?
and should i gate and sync my timer1 to the comparator?
asmboy



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PostPosted: Fri May 17, 2013 8:39 am     Reply with quote

every NRZ clock recovery I have seen uses a frequency
locking PLL that is:

a) harmonic insensitive
b) locked to 2f of the "data0" bit rate ( data1 rate=2f of data0 )

the 74hc4046 chip is an excellent datasheet for you to read and study
unless you are set on doing this the hard way. Very Happy Very Happy
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