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javick82
Joined: 12 Jul 2007
Posts: 43
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| PICDEM.net 2 ENC28J60 HW config with CCS TCP/IP Stack |
 Posted: Mon Jul 23, 2007 3:55 pm |
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I am looking to develop some firmware that needs to use ethernet. I have some experience with CCS's TCP/IP stack, and while it's basically what Microchip's is, I have worked with it and have had success with it. Has anyone modified the stack to include the picdem.net 2 board? Namely the TRIS configuration of the pins. I am having trouble with it.
Thanks for the help. |
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javick82
Joined: 12 Jul 2007
Posts: 43
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| Posted: Tue Jul 24, 2007 1:09 pm |
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Here is the code that I have. The top part is the code from CCS that specifies the I/O for the ENC28J60 on their development board. The bottom portion is the code from microchip configured for the picdem.net 2 board, I belive it is in Micro C18.
I would like to configure the CCS code so I can use the pinouts specified in the C18 code. I am having trouble understanding the last line of the CCS code, with the "#define mac_enc_spi_tris_init()..." and how this relates to the tristate configuration in the lower portion.
| Code: | //PIN I/O for ethernet development board, from CCS
#define PIN_ENC_MAC_SO PIN_C4 // PIC <<<< ENC
#define PIN_ENC_MAC_SI PIN_C5 // PIC >>>> ENC
#define PIN_ENC_MAC_CLK PIN_C3
#define PIN_ENC_MAC_CS PIN_D1
#define PIN_ENC_MAC_RST PIN_D0
#define PIN_ENC_MAC_INT PIN_B0
#define PIN_ENC_MAC_WOL PIN_B1
#define ENC_MAC_USE_SPI TRUE //due to an errata in the ENC28J60, you should always use HW SPI to assure that SPI clock is over 8MHz!
#define mac_enc_spi_tris_init() *0xF93=(*0xF93 | 0b11); *0xF94 = (*0xF94 & 0b11010111) | 0x10; *0xF95=*0xF95 & 0xFC
//PIN I/O for PICDEM.net 2 board, from Microchip (C18 compiler perhaps?)
// ENC28J60 I/O pins
#define ENC_RST_TRIS (TRISDbits.TRISD2) // Not connected by default
#define ENC_RST_IO (LATDbits.LATD2)
#define ENC_CS_TRIS (TRISDbits.TRISD3)
#define ENC_CS_IO (LATDbits.LATD3)
#define ENC_SCK_TRIS (TRISCbits.TRISC3)
#define ENC_SDI_TRIS (TRISCbits.TRISC4)
#define ENC_SDO_TRIS (TRISCbits.TRISC5)
#define ENC_SPI_IF (PIR1bits.SSPIF)
#define ENC_SSPBUF (SSP1BUF)
#define ENC_SPISTAT (SSP1STAT)
#define ENC_SPISTATbits (SSP1STATbits)
#define ENC_SPICON1 (SSP1CON1)
#define ENC_SPICON1bits (SSP1CON1bits)
#define ENC_SPICON2 (SSP1CON2) |
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PCM programmer
Joined: 06 Sep 2003
Posts: 21708
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| Posted: Tue Jul 24, 2007 3:42 pm |
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| Code: |
#define mac_enc_spi_tris_init() \
*0xF93 = (*0xF93 | 0b11); \
*0xF94 = (*0xF94 & 0b11010111) | 0x10; \
*0xF95 = *0xF95 & 0xFC
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The addresses given above refer to the TRISB, TRISC, and TRISD
registers, respectively.
The code is either clearing or setting bits in those registers.
For example, 0xF93 is the TRISB register. The line for it
sets bits TRISB.0 and TRISB.1 to a logic 1. This makes pins
B0 and B1 as inputs. It leaves the other bits unchanged.
An AND operation will clear any bits that are set to 0 in the bitmask.
An OR operation will set any bits high, that are set to a 1 in the bitmask. |
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