SPI problems - Serial data input

[mcman]

PIC: 18F87J10
Compiler: CCS 4.032

I'm communicating via a PIC SPI channel to serial flash devices from ST Microelectronics (M25P16 series).

On my prototyping system, I have an 18F8722 that works just fine. I can read/write to serial flash w/ no problems.

On my 18F87J10, I read 0 volts on the serial data input to the PIC. I've gone around and around checking the SPI clock and SDO feed to the flash and it looks fine. I've also hunted for PCB problems and can't find any.

I would like to rule out compiler and/or silicon issues given my PIC and compiler combo. If anyone knows of specific issues I would appreciate your feedback!

[PCM programmer]

This PIC has two MSSP modules. Which one are you using ? On which
pins ?

Post a short test program that shows the problem. Show all your #fuses,
#use, #include statements. The posted program should be compilable
"as is", without any editing. Make it be very short. (20 lines, max).

[mcman]

Here is some stripped down code that I've compiled and run.




#include <18F87J10.h>


#FUSES HS, DEBUG, NOXINST, NOSTVREN, NOWDT, NOPROTECT, WDT32, NOFCMEN, NOIESO, PRIMARY, NOWAIT, MCU, NOEASHFT

#USE DELAY(clock=20000000)


#define PWR_RUN PIN_D1
#define MEM_HLD PIN_D3
#define MEM_WR PIN_D7
#define MEM_SEL0 PIN_H4
#define MEM_SEL1 PIN_H5
#define MEM_SEL2 PIN_H6


#use fast_io(D)
#use fast_io(H)


void main()
{
char read = 0;

// setup SPI channel #2
SETUP_SPI2(SPI_SS_DISABLED);
SETUP_SPI2(SPI_MASTER | SPI_L_TO_H | SPI_CLK_DIV_4);


// setup Port D
//d0 spare 1 dig in
output_high(PWR_RUN); //d1 PWR_RUN 0 dig out
//d2 spare 1 dig in
output_high(MEM_HLD); //d3 MEM_HLD 0 dig out
//d4 SDO2 0 SPI #2 data output
//d5 SDI2 1 SPI #2 data input
//d6 SCK2 0 SPI #2 clock out
output_high(MEM_WR); //d7 MEM_WR 0 dig out
set_tris_d(0b00100101);


// setup Port H
//h0 spare 1 dig in
//h1 spare 1 dig in
//h2 spare 0 dig out
//h3 spare 0 dig out
output_high(MEM_SEL0); //h4 MEM_SEL0 0 dig out
output_high(MEM_SEL1); //h5 MEM_SEL1 0 dig out
output_high(MEM_SEL2); //h6 MEM_SEL2 0 dig out
//h7 spare 1 dig in
set_tris_h(0b10000011);


while(TRUE)
{

// write enable cmd
output_low(MEM_SEL0);
SPI_WRITE2(0x06);
output_high(MEM_SEL0);

// read status register
output_low(MEM_SEL0);
SPI_WRITE2(0x05);
read = SPI_READ2(0); // should observe write enable bit set
output_high(MEM_SEL0);

}
}

[mcman]

Update:

My bad. Flash takes data on rising edge of clock, not falling edge. I needed to add the SPI_XMIT_L_TO_H flag to the SETUP_SPI config options. Note that this flag isn't mentioned in the CCS compiler manual. Found it in the device header file.

Previously, on my proto board, I was just getting lucky since the data led the clock by 10s of nanoseconds. On the product board, there was a slight phase shift and the clock was leading data. Hence, the flash wasn't replying because it couldn't correctly 'hear' what it was being told.

With the correct option flag mentioned above, I have 100ns of margin either way based on 5MHz SPI clock.