SPI overflow

[robert]

Hi all,

I wonder if anyone has this info?

I am implementing a system (hardware not available yet) where I will be receiving SPI packets. Most of the time these packets will a fixed length but every 256 packets there will be an extra frame. Under normal conditions this extra frame is to be ignored and so for speed i was not going to read them from the SPI buffer. I will then get overflows. Does anyone know if this will cause any problems when I get the next packet. Do I have to reset any registers and how would I do that?

PS there are 20% dead time between packets for housekeeping.

Thanks and regards
Robert

[PCM programmer]

Read this slide show presentation from Microchip. It talks about
the SPI buffer overflow condition. See page 26:
http://ww1.microchip.com/downloads/en/devicedoc/spi.pdf

See Ttelmah's post near the end of this thread:
http://www.ccsinfo.com/forum/viewtopic.php?t=28698
He has posted some macros to disable and enable the SPI module
(per the info on page 26 of the slide show). You could do that,
with perhaps a short delay of a few microseconds in between
the disable/enable.

Also, Ttelmah's macros use register addresses for 16F PICs.
If you're using an 18F PIC, you will need to change the addresses.
Look in the SFR section in the data sheet to find the register addresses.

[robert]

Thanks PCM programmer.

Info looks good

Regards
Robert