Duty Cycle in the range of 45-55%

[Kit]

Hi,

Usually, when I want to use PIC to interface another IC, for the Clk or En pin of the device, I will send a Logic 1 and then followed by Logic 0 for each cycle.

for example,
output_high(PIN_STOP);
pulse();

where pulse is
void Pulse() {
output_high(PIN_B0),
delay_ms(100),
output_low(PIN_B0),
delay_ms(100),
}

In this way, I can get the job done, although the duty cycle of CLK pulse is not preserved.

Now I have to interface with an IC, which according to the datasheet,
CLK: The clock signal, coming from the external controller, must have a Duty Cycle within the Min/Max values defined by the specification (typically 50%).

What is the walkaround for this?

[PCM programmer]

You stated your problem in a very general way. By using Google
I have found the specifics of your problem.

You're using this chip:
http://www.onsemi.com/pub/Collateral/NCN6011-D.PDF
That chip is just a buffer and a level translator.

From that data sheet, I found that you want to interface to a SIM card.
Using Google, I found the specification here:
http://www.ttfn.net/techno/smartcards/gsm11-11.pdf
In section 5.4, on the Clock signal, it says this:

[MikeValencia]

You have a software-based duty cycle generator. Do you have interrupts enabled? This will skew your duty cycle, since delay_ms will get interrupted. The way you are doing it now, you are guaranteed at least 100ms between pulses, but other ISRs can add to this time, since you're effectively freezing the delay_ms() function loop when an isr hits.

[Kit]

PCM Programmer,

Cool! you can trace what chip I am using I am using NCN6010, though, not far from your guessing. I admire you now hoho

45%-55% is when I want to change the operating speed of the SIM card.


MikeValencia,

Yup, this is what i worry about. Besides ISR, since the uC executes the code in sequential order, I might execute some instructions in between two pulses.

This will alter the duty cycle. in worst case, it might out of the 40-60 % range.

[MikeValencia]

I browsed thru the PWM module documentation, and found that the slowest PWM frequency you can have is TMR2/16. What is the fastest frequency allowed by the device you are talking to?

Your bitbang of 100ms on and 100ms off can be done in a TMR0 isr though, where you can have prescalers up to /256 i think. This will also suffer a little bit skew (due to simultaneous interrupts being serviced, and the isr's latency in saving registers, unless you use a fast interrupt).

The least software intensive way to do it though would be to shoot out a 50/50 duty cycle on the PWM pin, so long as the minimum frequency of the PWM that your PIC/crystal speed combination PWM generator is not too fast for the other IC's specs.

-Mike