PIC18F2550 SPI SPEED

[rudy]

Hi there.

I am using a 18F2550 to drive a 320x240 LCD, I am not sure this configuration below gives me the fastest SPI speed, can you help me?

[Ttelmah]

With your posted setup, you are not running at 48MHz.

Now I assume you have a 20MHz crystal?.

So 20MHz/5 = 4MHz feeding the PLL. The PLL then gives 96MHz to the
USB. You are then assuming that CPUDIV2 is the correct setting to get
48MHz to the CPU. Not the case.
We run here into a problem. The CPUDIV fuses have different meanings
according to whether you use the PLL or don't.

[temtronic]

I have to ask, what is the maximum speed that the LCD module can handle ??
Say the datasheet says 'SPI data transfer ... max of 3.4MHZ', then ANYTHING over that will not work, you'll have to setup the SPI peripheral to say 3 MHz (probably some close 'binary' speed based on PIC clock though).
Just because the PIC hardware can go fast doesn't mean the peripheral (LCD module) can. I've got a PIC running 64MHz but the serial interface is actually 24 baud. Yes, twenty four baud.

[rudy]

Ttelmah, thanks.

By the way, yes, I am running with 20Mhz crystal.

When I look the datasheet, the primary oscillator goes directly to a prescaler, and after that, it goes straight to PLLDIV block. Now, moving for table 2-3 on page 32 of the datasheet, we have 20MHZ crystral + PLL5 + CPUDIV2 = 48Mhz clock frequency.

Now I really don't know what is the frequency I am working with. I know it may be a little abuse from me, but can you write the correct configuration for me, both for SPI and CLOCK frequency at the higher levels?

I appreciate that!

Regards.

[rudy]

[Ttelmah]

You need to look again at the datasheet.

The clock can come from the crystal, two different routes. The first, is
oscillator directly to CPUDIV. This has 'XT, HS, EC, ECIO' against the
CPUDIV block.
Then you have the PLL route. Here the clock feeds a divider, that has
to be chosen to give 4MHz (note saying 4MHz input only in the diagram).
This then feeds the 96MHz PLL. This then routes right to the PLL circuitry,
but also down with the note 'HSPLL, ECPLL, XTPLL, ECPIO'. This is the route
the clock goes when these are selected. This again feeds the CPUDIV
divider, but whereas the first route to this has 11=4, 10=3, 01=2, and
00=1, this second route to the divider has it's divisions change, and has
11=6, 10=4, 01=3, and 00=2.
Now the CCS CPUDIV fuse settings give the 00, 01,10, and 11 settings to
this divider, but the divisions that result differ according to what clock
'route' you use.
If you look, table 2-3, does not use the term CPUDIV2. It says the that
to get 48MHz, you have to use the fuse pattern 00, which then gives
/2. If you look a couple of lines higher when using HS, the 00 fuse
pattern gives /1. Unfortunately (designed to confuse I think), CCS elected
to call the fuse patterns by the divisions you get for XT, HS etc. So when
using the PLL, the /2 fuse pattern is CPUDIV1.
It is a really critical bit of understanding needed for the 2550/4550 setup.
You are currently actually running at 32MHz.

Be very aware though that the speed you can actually run the SPI
depends massively on the wire lengths. Have a system here which 'on
the bench', happily runs SPI at 8MHz. However in the real units, with
a 250mm cable between the PIC and the display controller, had to drop
the clock to just 3.4MHz for reliability...

[Ttelmah]

The big glaring thing here is how you are handling the voltage translation
between the 2550, and the LCD?.
The 2550, is a 5v PIC. 4.2v minimum for full speed operation. The
LCD is a 3.3v maximum device. You need level translation buffers
between these chips.

[rudy]

THANKS.

Quite complex. Now I changed CPUDV2 to CPUDIV1, and increased my LCD freshrate a lot!

I think this is the maximum I can get from the 18F2550.

It is much better now!

Regards!

[rudy]

Just for the record!

By the way, with this change, and increase the clock speed, I could get rid of an old problem that bores me for so many times. With the old configuration or CPUDIV2 (running at 32MHz as you told me), all the communications between PIC18F2550 and LCD module results in a huge interference in the RDA5807 FM module, somehow, the communication frequency was in a frequency that causes undesirable noises in the IF frequency of the RDA5807. I was quite sure that the old configuration was the best frequency clock I could get, based on that table on datasheet. If I reduce the clock frequency, the interference in the RDA5807 simply vanishes, but the LCD update frequency becomes even worse. Thanks to you, I solved two problems with a single shot!

Really, really thank you! All of you again!

Regards

[rudy]

[vtrx]

Could you tell me if with this configuration I have the maximum speed using SPI?
I use USB.

4MHZ xtal.

[rudy]

Hi,

I just solved my problem, but I will try!

With 4mhz crystal, you may try: