|
|
View previous topic :: View next topic |
Author |
Message |
Ttelmah
Joined: 11 Mar 2010 Posts: 19498
|
|
Posted: Tue Feb 26, 2019 1:39 am |
|
|
A row is 192 bytes. 64*3 byte words. Not 64*2.
Each instruction, is 3 bytes out of a 4 byte 'space'. The row is 64 of these
'spaces'.
The problem in the erratum, happens when data is written, not on the
erase. |
|
|
canadidan
Joined: 13 Feb 2019 Posts: 24
|
|
Posted: Wed Feb 27, 2019 8:49 am |
|
|
Good news - I think I solved it.
rom_write.c
I discovered the rom_write library in Compiler V5.044 - it wasn't in V4.106.
This library includes the rom_modify() function. This function handles page buffering, which was something I unsuccessfully tried to implement myself.
It still uses write_program_memory() in its rom_flush() function, but it does it by page - doubtful that it uses word programming method.
Results
I ran it overnight, and completed 1000 cycles without error.
To validate that the data was properly written, I have a few points:
* I still run the erase routine first. Thus, if rom_modify() didn't write the correct data, my application would have little chance of working.
* I did a ROM dump before and after a firmware upgrade, then compared the data. The updated data was properly recorded in the "after" dump. Verified this with 3 FW versions.
Drawback
Since it buffers the flash writes, my existing verification code doesn't work since it expects the HEX line to already be written. However, adding a verification stage to rom_flush() would be easy enough.
Going Forward
I will do more testing, and likely have to re-qualify a lot of the system. However, rom_modify() appears to be a better function to use than write_program_memory() for large data writing operations.
Helpful note to others: Since rom_modify() only flushes to ROM after a page boundary change, you will need to run rom_flush() at the end of your upgrade routine to ensure all data is written. |
|
|
temtronic
Joined: 01 Jul 2010 Posts: 9221 Location: Greensville,Ontario
|
|
Posted: Wed Feb 27, 2019 10:43 am |
|
|
OK... you got ANY hair left ??? Man this has been one nasty journey for you !! |
|
|
PCM programmer
Joined: 06 Sep 2003 Posts: 21708
|
|
Posted: Wed Feb 27, 2019 11:26 am |
|
|
I admire that you didn't give up, you kept at it until the problem was solved. |
|
|
canadidan
Joined: 13 Feb 2019 Posts: 24
|
|
Posted: Wed Feb 27, 2019 12:27 pm |
|
|
It's not quite resolved!
The firmware was originally programmed with V4.106.
I ported the BIOS to V5.044 fine, but the firmware had a bunch of bugs with the newer compiler.
The test last night was using V5.044 generated BIOS, and firmware HEX from V4.106.
I tested this morning using V4.106 generated BIOS and it failed.
-> I will now retest with V5.044 generated BIOS to confirm fix. If so, the solution is twofold:
1. Use rom_modify()
2. Use V5.044 compiler
** Stay tuned ***
@PCM programmer - I have no choice, this is my 8-5 job!
@temtronic - still some hair, but I'm only young yet |
|
|
Ttelmah
Joined: 11 Mar 2010 Posts: 19498
|
|
Posted: Thu Feb 28, 2019 12:09 am |
|
|
Obviously be aware that you are going to hit the 'life' limit on your test
chip fairly soon....
The 'guaranteed' life is only 100 cycles. 1000 is the 'typical'. |
|
|
canadidan
Joined: 13 Feb 2019 Posts: 24
|
|
Posted: Thu Feb 28, 2019 7:29 am |
|
|
@Ttelmah - this is true, good point. However, wouldn't failure only occur in the blocks being erase/written? Even after 1000 cycles, the device ID block shouldn't become corrupted right?
Compiler V4.106 - 172 cycles before device ID corrupted
Compiler V5.044 - 1735 cycles before device ID corrupted
To confirm - I will start with two brand new PICs and test each version of the code. |
|
|
Ttelmah
Joined: 11 Mar 2010 Posts: 19498
|
|
Posted: Thu Feb 28, 2019 8:55 am |
|
|
Yes. I was simply warning that the 'test' chip you have run 1000 cycles on,
was likely to soon start failing... |
|
|
canadidan
Joined: 13 Feb 2019 Posts: 24
|
|
Posted: Fri Mar 01, 2019 8:53 am |
|
|
Verdict
After a race to the death with two brand new ICs, my original hypothesis doesn't hold up:
Hypothesis: along with using rom_modify(), I need to port my code from V4.106 compiler to V5.044.
Experiment: two brand new PIC24HJ256GP210 ICs, one with FW compiled using V4, one compiled with V5. Continuous firmware upgrade cycles.
Results:
* Original code: ID corruption after average ~165 cycles (range: 1 to 600)
* rom_modify, V4 (new IC): ID corruption after ~800 cycles
* rom_modify, V5 (new IC): ID corruption after ~1700 cycles
* rom_modify, V4 (new IC #2): still going after 1900+
Conclusion:
* Results suggest compiler version didn't make a difference.
* Skipping the erase cycle, or page aligning it, also had no measurable impact on ID corruption.
* Using rom_modify() has had the only measurable impact.
To minimize overall design impact, I will stay with the "stable" V4.106 environment but bring the rom_write.c library into my project. |
|
|
Ttelmah
Joined: 11 Mar 2010 Posts: 19498
|
|
Posted: Fri Mar 01, 2019 9:38 am |
|
|
The danger with this is that the internal code for write_program_memory
may well also have been changed in the V5 compiler, so rom_modify
may not work as well with 4.106. |
|
|
canadidan
Joined: 13 Feb 2019 Posts: 24
|
|
Posted: Fri Mar 01, 2019 9:49 am |
|
|
I agree, and I wish we had transparency into that particular function.
My primary goal was to reduce instances of the Device ID becoming corrupt upon the very first upgrade. Of the 5 units tested with the new code, none have corrupted upon the first try.
We are aiming for a new generation hardware design by end of year, and I'll be going for something ARM Cortex-based I think. Still have to maintain this old design! |
|
|
Ttelmah
Joined: 11 Mar 2010 Posts: 19498
|
|
Posted: Fri Mar 01, 2019 11:22 am |
|
|
You could do a simple compare of the assembly generated. If it is the
same in V4, 'hurrah', if not then I'd say you really need to be compiling
with the V5 compiler. |
|
|
canadidan
Joined: 13 Feb 2019 Posts: 24
|
|
Posted: Fri Mar 01, 2019 3:55 pm |
|
|
Great idea!
The initial setup is the same (no surprise):
Code: |
// V4.106
//write_program_memory(_romw_curr_page, _romw_buffer, sizeof(_romw_buffer)); //write modified block
284E2 805C60 MOV B8C,W0 : W0 = B8C
284E4 805C71 MOV B8E,W1 : W1 = B8E
284E6 20B902 MOV #B90,W2 : W2 = B90
284E8 208003 MOV #800,W3 : W3 = 800
284EA 0276A8 000002 CALL 276A8 :
|
Code: |
// V5.044
//write_program_memory(_romw_curr_page, _romw_buffer, sizeof(_romw_buffer)); //write modified block
2862E: MOV C0C,W0
28630: MOV C0E,W1
28632: MOV #C10,W2
28634: MOV #800,W3
28636: CALL 276F0
|
Now, loading the write latches:
Using my limited ASM knowledge, I observe:
* A sequence that runs before and after, looks like it takes WREG6 and WREG9 and temporarily stores them in the stack during programming (not in datasheet)
* TBLRD before some TBLWT with V4.106 (seems deprecated - not in datasheet)
* MOV #FFFF,W4 before some TBLWT with V5.044 - move W4 into #FFFF (which isn't writable memory? - not in datasheet)
* In the middle, it checks if W1 overflowed, and increments "0032" (0x20 - SPLIM, Stack Pointer Limit Register). Since I know I will only ever write a page (512 instructions = 0x400 addresses = 0x600 byte array) and that it should never exceed that stack pointer (not in datasheet)
If we dig into the call which sets the Write Key:
Two differences:
* Nested interrupts are disabled, while disabling interrupts? (not in datasheet)
* Rather than using AND with INTTREG (0xE0) and SR, it uses IOR (this is how the datasheet does it, except they only perform IOR SR, without #E0)
Edit: updated my analysis. Most of the differences aren't documented in the datasheet, and must be CCS specific implementations. I'm not overly worried about those, since my testing has shown dramatic improvement despite the older compiler.
Critical differences such as catching stack pointer overflow and disabling nested interrupts don't concern me for this design - the data size is always the same, the environmental conditions at the beginning of the process are always the same, and I don't use nested interrupts in this code.
Agreed - these are not small differences, but for this design we can get by.
Last edited by canadidan on Mon Mar 04, 2019 8:52 am; edited 1 time in total |
|
|
newguy
Joined: 24 Jun 2004 Posts: 1907
|
|
Posted: Fri Mar 01, 2019 5:00 pm |
|
|
You'll have to dig through the errata first, then the data sheet. Microchip might also have some app notes dealing with the issue. Do some reading and the assembly will start to make sense.
PS: want a job? Your attention to detail is to be commended. |
|
|
|
|
You cannot post new topics in this forum You cannot reply to topics in this forum You cannot edit your posts in this forum You cannot delete your posts in this forum You cannot vote in polls in this forum
|
Powered by phpBB © 2001, 2005 phpBB Group
|