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AD8402 digital pot - sending 10bits via SPI?

 
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rcooke



Joined: 23 Feb 2011
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AD8402 digital pot - sending 10bits via SPI?
PostPosted: Sun Apr 10, 2011 1:31 pm     Reply with quote

Hi Folks,

In my application I am forced to use the HW SPI due to conditions out of my control. I need to write 10 bits to the chip 2 bits of address and 8 bits of data. I can't use the CCS supplied 8400.c library because that uses a software SPI.

Looking at the 8402 datasheet is seems like I can send it 16 bits with the MSB 6 bits set to zero. It seems like the chip will load the register when the /CS line goes high so only the last 10 bits are actually loaded. Does this make sense?

Thanks,

Richard
bkamen



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PostPosted: Sun Apr 10, 2011 1:41 pm     Reply with quote

That's pretty bizarre...

I would just write a software routine to handle it since doing a double write (16bits) doesn't seem to be an option.

How bizarre.

-Ben
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rcooke



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PostPosted: Sun Apr 10, 2011 1:46 pm     Reply with quote

I don't understand why you say it is bizarre. The hardware team designed the circuit in such a way that I am forced to use the hardware SPI function on the chip (18F24K22). We have other devices that I have to communicate with via the SPI bus.

Richard
PCM programmer



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PostPosted: Sun Apr 10, 2011 1:48 pm     Reply with quote

Quote:

Looking at the 8402 datasheet is seems like I can send it 16 bits with the
MSB 6 bits set to zero.

Ttelmah says the same thing in the 3rd post in this thread:
http://www.ccsinfo.com/forum/viewtopic.php?t=32681
rcooke



Joined: 23 Feb 2011
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PostPosted: Sun Apr 10, 2011 2:05 pm     Reply with quote

PCM,

Thanks for the heads-up. I searched the forum but didn't do a very good job. I just wanted a second opinion and you pointed me to one. That's the beauty of this forum.

Richard
FvM



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PostPosted: Mon Apr 11, 2011 3:19 am     Reply with quote

There's a simple guideline. A device declared SPI compatible will always be able to communicate in multiplies of 8 bits. As many simple SPI devices, the AD8402 doesn't care how many bits have been shifted in front of the last 10 bits before the /CS rising edge.
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