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eskachig
Joined: 27 Mar 2009
Posts: 8
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| (Yet another) quick ADC question, 18LF8722 |
 Posted: Fri Mar 27, 2009 4:58 pm |
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Hi everyone, this is my first post here, this is an awesome forum with a huge wealth of information and it's been a giant help to me - I'm a total n00b when it comes to microcontrollers. I have a couple of slightly theoretical questions.
I'm using a DLP design board DLP-245PL-G with a 18LF8722 microcontroller. It's advertized as a 24 Mhz setup - meaning that it has a 6Mhz crystal that can be used to drive the PIC at 24Mhz with PLL.
The datasheet for the PIC says that 22Mhz is max for this low power model. I know PICs in general are pretty resiliant when it comes to some slight overclocking, but am I going to have any trouble? To complicate matters more it looks like we're providing full 5V to run it, instead of the minimum 3.
Moving on to my real question. I'm trying to correctly set up my ADC converter. The Tad vs device frequency table in the data sheet has this:
| Code: | Operation PIC18FXXXX PIC18LFXXXX(4)
2 TOSC 2.86 MHz 1.43 kHz
4 TOSC 5.71 MHz 2.86 MHz
8 TOSC 11.43 MHz 5.72 MHz
16 TOSC 22.86 MHz 11.43 MHz
32 TOSC 40.0 MHz 22.86 MHz
64 TOSC 40.0 MHz 22.86 MHz |
This implies that I should use
| Code: | | setup_adc(ADC_CLOCK_DIV_32); or setup_adc(ADC_CLOCK_DIV_64); |
It also has this blurb:
For correct A/D conversions, the A/D conversion clock
(TAD) must be as short as possible, but greater than the
minimum TAD (see parameter 130, Table 28-27 for
more information).
Table 21-1 shows the resultant TAD times derived from
the device operating frequencies and the A/D clock
source selected. <- this is what I quoted above
So I go to the table it talks about and look up those times and get
PIC18FXXXX min-0.7 max-25.0(1) μs TOSC based, VREF ≥ 3.0V
PIC18LFXXXX min-1.4 max-25.0(1) μs VDD = 2.0V;TOSC based, VREF full range
Aquisition time 1.4 μs at 50Ω, but it looks like worst case scenario is 2.4us
Now when I use the project wizard to set everything up (I have to use 18F8722 as a device because it doesn't have a low power version available) I can set up the AD clock, the closest I can get to those values is 2.7 μs - the multiplier that the wizard gives me is ADC_CLOCK_DIV_16, which disagrees with the datasheet. Is the wizard correct in this case?
Also the wizard lets me select aquisition time (which I set at 2.7), with the result function being
| Code: | | setup_adc(ADC_CLOCK_DIV_16|ADC_TAD_MUL_16); |
With the aquisition time in there, does that mean I no longer have to wait after setting the channel? Kind of like this:
| Code: | set_adc_channel(channel);
//delay_us(10); // no longer needed
read_adc(); |
Sorry about this mess, I'm very confused at the moment, and if someone can at least point me in the right direction I'd be very grateful. |
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PCM programmer
Joined: 06 Sep 2003
Posts: 21708
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| Posted: Fri Mar 27, 2009 5:34 pm |
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| Quote: | I'm using a 18LF8722 microcontroller
The datasheet for the PIC says that 22Mhz is max for this low power model.
we're providing full 5V to run it, |
Where does the data sheet say it's limited to 22 MHz at 5v ?
http://ww1.microchip.com/downloads/en/DeviceDoc/39646c.pdf |
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eskachig
Joined: 27 Mar 2009
Posts: 8
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| Posted: Fri Mar 27, 2009 8:58 pm |
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P 277 table for clock times vs max frequency. Maybe I took it to mean more than it did.
This is really my first foray into microcontrollers - I'm a .NET developer, my typical work is about as far removed from this as it gets. There is a whole lot of information to digest, forgive me if I ask something stupid - I really do try to search the forums, data sheets, and CCS documentation when I run into trouble before posting. |
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Ttelmah
Guest
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| Posted: Sat Mar 28, 2009 4:16 am |
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Key part is figure 28.3.
Last line above the note.
So long as you are using the internal memory, and your supply voltage is greater than:
((24-4)/16.36)+2 volts = 2.367v, the chip is certified to run at your 24MHz
The LF devices have significant changes to the ADC, increasing the internal resistances, and doubling the required sample times relative to the normal parts. Unfortunately, this does mean that the ADC may well be a problem.
I'd suggest using the internal RC instead of the master clock, and putting the chip to sleep for the conversion. This will give a Tad, on the LF chips in the order of 3uSec, and is actually the most accurate way to work. A lot depends on what accuracies you actually need. The specified clocks, are 'maxima', to achieve the full specified accuracy of the ADC. Going beyond the figure, doesn't stop the ADC working, but degrades it's accuracy.
So you have two choices:
1) Overclock the ADC a fraction, and accept the (very slight in your case), loss of accuracy.
2) Use the RC clock, and put the chip to sleep.
Best Wishes |
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eskachig
Joined: 27 Mar 2009
Posts: 8
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| Posted: Sun Mar 29, 2009 3:24 pm |
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| Ttelmah wrote: | Key part is figure 28.3.
Last line above the note.
So long as you are using the internal memory, and your supply voltage is greater than:
((24-4)/16.36)+2 volts = 2.367v, the chip is certified to run at your 24MHz
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Ok, awesome!
| Quote: | | The LF devices have significant changes to the ADC, increasing the internal resistances, and doubling the required sample times relative to the normal parts. Unfortunately, this does mean that the ADC may well be a problem. |
Not so awesome.
| Quote: |
1) Overclock the ADC a fraction, and accept the (very slight in your case), loss of accuracy.
2) Use the RC clock, and put the chip to sleep. |
I don't think I can put the device to sleep during ADC because I have to have it drive a (software) PWM on a pin. With my settings am I really overclocking the ADC? According to the timing values in table 28-27 the clock settings I've selected should clear the minimums by a large margin. Would it help to slow them down even more? In my own tests it didn't seem to make any difference whatsoever, but I wasn't particularly rigorous about it.
Also, am I setting up the hardware Tacq delay correctly or do I still need a manual delay after channel selection? |
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