prwatCCS
Joined: 10 Dec 2003
Posts: 70
Location: West Sussex, UK
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| Write_eeprom() |
 Posted: Thu Sep 18, 2008 10:22 am |
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I am using PCWH 3.249 and PCWHD 4.073.
PIC 18F252
At background in my code I call write_eeprom(), but as it masks interrupts for the entire time it takes to write data to the internal eeprom, I have difficulty in servicing other interrupts adequately.
From the compiler I get (same results from both versions of compiler)
| Code: |
CCS compiler code masking interrupts for duration of EE write cycle
.................... write_eeprom(offset,data);
*
0C14: MOVFF 136,FA9
0C18: MOVFF 137,FA8
0C1C: BCF FA6.6
0C1E: BCF FA6.7
0C20: BSF FA6.2
0C22: MOVFF FF2,00
0C26: BCF FF2.6
0C28: BCF FF2.7
0C2A: MOVLB F
0C2C: MOVLW 55
0C2E: MOVWF FA7
0C30: MOVLW AA
0C32: MOVWF FA7
0C34: BSF FA6.1
<< >> why is the re-enable of interrupts not here ??
0C36: BTFSC FA6.1 ** this line spins until write complete
0C38: BRA 0C36 **typ 4ms according to datasheet
0C3A: BCF FA6.2
0C3C: MOVF 00,W ** this is the bit that re-enables irq
0C3E: IORWF FF2,F
....................
.................... }
0C40: MOVLB 0
0C42: RETLW 00
....................
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My analysis of the 18F252 data sheet suggests interrupts only need to be disabled whilst we "unlock" the device and start the actual write cycle.
Is there a known switch in the CCS compiler that re-enables irq at the point I have marked above ??
I have tried the #device WRITE_EEPROM=ASYNC, but that seems to result in unreliable writes to the EEPROM. It places the check for write competion on entry to the code, which means I can exit and attempt a read BEFORE the write has actually completed ....
any ideas
regards
_________________
Peter Willis
Development Director
Howard Eaton Lighting Ltd UK |
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