Disabling interrupts when writing to data EEPROM

[lindsay.wilson.88]

Just spent the morning tearing my hair out wonder why my nice regular timer1 interrupts were screwing up whenever I wrote anything to the data EEPROM and, sure enough, I should have read the datasheet ;-) Interrupts are disabled when writing to the EEPROM. Now I know the reason, I can work around it. Seems to take around 3-4ms for a single byte write.

However, could someone explain why exactly this is required? The best I can find online is that once a write has started, other EEPROM-related stuff has to happen within a certain time for the write to be successful, and any interrupt would mess this up. Is that essentially it?

[temtronic]

yes......
You have to remember PICs, like 99.44% of all micros can only do ONE operation at a time...ask it to do too much and oopsy....
Some (most ? ) EEPROMs have a faster method, usually a 'block' of data. Saving ONE byte at a time will be time consuming, as you've found out.
Depending on your application, maybe you can use this 'block' write mode ?

For me, I used an RTC modules 8 bytes of battery backed RAM for the 4 or 5 often changing data that I needed to be stored.

Not all PICs are the same of course so sadly you do HAVE to read a few 100 pages or so to figure some things out.
In the 'dinosaur' days, I'd red the datasheet while the PIC was being erased under a bath of UV radiation......

[Ttelmah]

The EEPROM and the internal flash memory are all on the same substrate.
It's not a separate chip.
Now the Flash memory has only a drive for a row on the memory, while the
EEPROM has a separate drive for each cell. Hence on the flash you do a
'row write' for the same time as a cell write on the EEPROM.
The EEPROM write requires generating Vpp, and actually performing a
write cycle to the memory. Now you cannot read while you are writing,
and since it is all on the same substrate, this means the CPU cannot
read from it's program memory during this time. Attempting to read during
a write, actually activates paths inside the chip that can lead to early
erasure. Effectively the cell you are reading gets connected by the internal
diode structures to the Vpp.
That it takes 3+mSec, means this is quite an old chip family. The newer
chips can perform the write in typically half this time.
A couple of the smaller PIC's do have the EEPROM built as a separate
die internally. On these you effectively have to perform an I2C EEPROM
write cycle. Slower, but has the advantage the chip can keep running.
If you want to use EEPROM without the CPU pause, then add an external EEPROM....