Need interrupt diagram for PIC16F684

[srikrishna]

Hello guys i need INTERRUPT LOGIC diagram for PIC16F684. I can not find it in the datasheet.

[Ttelmah]

Each enable bit is fed into an AND gate with it's interrupt flag as the
other input. The output of each of these gates is fed into a multi input
OR gate. The output of this is then fed into an AND with the GIE to give the
PIC logic interrupt bit (actually there are a couple of inversions NOR and
NAND, but this is the 'logic' effect).

At the start of Q1 of each instruction, it tests the logic interrupt bit. If this
is set it does not start the instruction fetch.
Instead it clears the GIE, and triggers a new Q1 instruction fetch
cycle for a call instruction to the address contained in the peripheral
interrupt vector.
So the instruction pipeline gets a single cycle bubble when an
interrupt triggers.

When you perform the RETFIE at the end of the interrupt, it returns to
the instruction where the interrupt triggered, _and then sets GIE
back on_. This means that if another interrupt has triggered it'll
occur in phase 1 of the following instruction.

Because GIE is 'relied' on in the PIC to prevent interrupts triggering
inside one another, this is why you should never set GIE inside an
interrupt handler. Instead using the RETFIE instruction to do this.

This site has the logic diagram for the 16F877. Your chip has fewer
interrupts, but the basic logic is the same.

<http://www.microcontrollerboard.com/pic_interrupt.html>

[PCM programmer]

[temtronic]

re:

[Ttelmah]

That's hilarious....

He must like me, have the older 2004 data sheet. Guess what isn't there
in this one!....

Classic.