| View previous topic :: View next topic |
| Author |
Message |
[email protected]
Joined: 24 Mar 2010
Posts: 24
|
| watchdog problem when moving to 18F86J90 |
 Posted: Mon Oct 26, 2015 5:03 am |
 |
|
Hi,
Our company used 18F85J90 for the past 5 years with PCH 4.099.
Lately we moved to 18F86J90 (for more memory) with the same PCH version.
Suddenly we observe issue with WDT not waking up device from sleep (or waking up from sleep does not start timer0 - still not sure which one of the two causes the issue).
Is there any known issue about that?
Upgrading to new PCH will require a lot of system modifications to keep backwords compatibility which is not on schedule now.
Regards,
Gil
_________________
Gil F. |
|
 |
temtronic
Joined: 01 Jul 2010
Posts: 9221
Location: Greensville,Ontario
|
|
| Posted: Mon Oct 26, 2015 5:48 am |
|
|
If your code is 100% the same.. dump the listings for both the 85 and 86 chips.The ONLY difference should be the 'PIC type' in the first line.
Odds are the compiler isn't configuring the 86 'as required'. That should be obvious in the listing.
Also be sure to have the databook nearby to confirm addresses,register settings, etc. !
Jay |
|
|
[email protected]
Joined: 24 Mar 2010
Posts: 24
|
|
| Posted: Wed Oct 28, 2015 5:06 am |
|
|
Hi Jay,
i equalized both codes to be perfectly by 100% the same (except for the line: #include 18F8XJ90.h which are different).
Yet, i see difference in two sections:
section 1: in the config fuses:
18F85J90:
Word 1: F4A1 NODEBUG NOXINST STVREN WDT NOPROTECT
Word 2: FBC0 HS WDT2048 FCMEN IESO INTRC INTRC_IO
Word 3: F100 CCP2C1
18F86J90:
Configuration Fuses:
Word 1: F4A1 NODEBUG NOXINST STVREN WDT NOPROTECT
Word 2: FBDA WDT2048 FCMEN IESO INTRC HPT1OSC T1DIG
Word 3: F1F2 CCP2C1 RTCOSC_T1
And section 2 initial code:
18F85J90:
........... #device PIC18F85J90
MOVFF FF2,0E
BCF FF2.7
CLRF FF7
ADDLW 18
MOVWF FF6
MOVLW 01
ADDWFC FF7,F
TBLRD*+
MOVF FF5,W
BTFSC 0E.7
BSF FF2.7
RETURN 0
DATA 01,02
DATA 04,08
DATA 10,20
DATA 40,80
..
..
.. (more code)...
................ #list
................
................ #include "global.h"
18F86J90:
... Nothing
......
................ #list
................
................ #include "global.h"
Can these differences affect timer0 (which is causing the issue)?
How can i equalize configuration bits in both controllers if they are originally different?
Regards,
Gil
_________________
Gil F. |
|
|
[email protected]
Joined: 24 Mar 2010
Posts: 24
|
|
| Posted: Wed Oct 28, 2015 5:29 am |
|
|
...and the #fuses are exactly same for both controllers:
................ //#fuses HS, NOWDT, NOPROTECT, INTRC
................ #fuses HS
................ #fuses NOPROTECT, INTRC
................
................ // adding the watch dog timer ...
................ // 4mS * 2048 = 8192 mS
................ #fuses WDT, WDT2048
................
................ #ifndef _GLOBAL_H_
................ #define _GLOBAL_H_
................ //#use delay(clock=8M, oscillator)
................ #use delay(internal=8M)
_________________
Gil F. |
|
|
Ttelmah
Joined: 11 Mar 2010
Posts: 19496
|
|
| Posted: Wed Oct 28, 2015 5:40 am |
|
|
| Why are you selecting both the HS oscillator, and the INT_RC?.... |
|
|
[email protected]
Joined: 24 Mar 2010
Posts: 24
|
|
| Posted: Wed Oct 28, 2015 6:36 am |
|
|
Yes you are right. That's the reason why i removed it in the 86. Yet, i am not sure if the initial code and/or the configuration bit differences can affect the watchdog or timer0.
Gil
_________________
Gil F. |
|
|
temtronic
Joined: 01 Jul 2010
Posts: 9221
Location: Greensville,Ontario
|
|
| Posted: Wed Oct 28, 2015 7:33 am |
|
|
this....
Word 2: FBC0 HS WDT2048 FCMEN IESO INTRC INTRC_IO
doesn't look right
shouldn't be able to select INTRC INTRC_IO
I assume that INTRC_IO overrides INTRC as it's the last option in the line?
You need to look at the datasheet and confirm the bits in the registers are correct for every option in the 'fuses' configuration.
Words 2 and 3 are not the same.....
IF the PICs have the same 'fuses' then the Words should be the same....
that's why you need to read the datasheets, write out the configs and compare the words.
Also maybe the compiler is setting a wrong bit .
Jay |
|
|
[email protected]
Joined: 24 Mar 2010
Posts: 24
|
|
| Posted: Wed Oct 28, 2015 8:10 am |
|
|
Again, the wrong configuration bits are in the 85 controller which works fine. The problem is with controller 18F86J90.
Do you know why initial code is different?
Gil
_________________
Gil F. |
|
|
Ttelmah
Joined: 11 Mar 2010
Posts: 19496
|
|
| Posted: Wed Oct 28, 2015 8:37 am |
|
|
That is not 'initial code'. It is the code for a const table in the ROM. I'd suspect one of the chips has the #nolist option in the compiler 'remmed' out in the .h file, so this is visible (it is normally hidden).
There are differences in the chips, particularly things like the PLL, which will need some small configuration changes. The older chip also has a couple of errata that the compiler will probably add the code to fix.
Realistically, start by tidying up your configurations and setting them up correctly for each chip separately. Then write a small program that just uses the timer, sleep and watchdog, and see if you can duplicate the fault. If so, you then have something that can be posted, to give up a 'hope' of helping. At the moment it is like trying to drink coffee with an eye-dropper...
The obvious thing is that the later chip is actually going fully to sleep, not to idle mode. As such the watchdog would then stop. So how are you actually setting up the sleep?. |
|
|
Ttelmah
Joined: 11 Mar 2010
Posts: 19496
|
|
| Posted: Wed Oct 28, 2015 9:43 am |
|
|
The sort of test I have in mind, is something like this:
| Code: |
#include <18F86J90.h>
#device adc=8
#FUSES WDT
#FUSES WDT1024 //Watch Dog Timer uses 1:1024 Postscale
//gives a 4 second delay, so we can see if the chip is sleeping
#FUSES NODEBUG //No Debug mode for ICD
#FUSES NOXINST //Extended set extension and Indexed Addressing mode disabled (Legacy mode)
#FUSES STVREN //Stack full/underflow will cause reset
#FUSES NOPROTECT //Code not protected from reading
#FUSES FCMEN //Fail-safe clock monitor enabled
#FUSES IESO //Internal External Switch Over mode enabled
#FUSES PRIMARY //Primary clock is system clock when scs=00
#FUSES RESERVED //Used to set the reserved FUSE bits
#FUSES INTRC_IO //Internal RC Osc, no CLKOUT
#use delay(clock=8000000)
#use rs232(baud=9600,parity=N,xmit=PIN_C6,rcv=PIN_C7,bits=8, errors)
void main()
{
setup_oscillator(OSC_8MHz | OSC_IDLE_MODE); //must select idle mode to keep
//watchdog running
setup_adc_ports(NO_ANALOGS);
setup_spi(FALSE);
setup_lcd(LCD_DISABLED);
setup_timer_0(RTCC_INTERNAL);
setup_timer_1(T1_DISABLED);
setup_timer_2(T2_DISABLED,0,1);
setup_comparator(NC_NC_NC_NC);
setup_vref(FALSE);
printf("Starting\n");
restart_wdt();
sleep();
delay_cycles(1);
printf("Awake\n");
printf("Timer 0 = %ld\n", get_timer0());
restart_wdt();
delay_ms(1000);
restart_wdt();
printf("Timer 0 = %ld\n", get_timer0());
while (TRUE)
restart_wdt();
}
|
The delay from the watchdog, should be obvious (just over 4 seconds from the first message), and you can see if the timer is running. |
|
|
[email protected]
Joined: 24 Mar 2010
Posts: 24
|
|
| Posted: Wed Nov 11, 2015 8:03 am |
|
|
ok. thanks
_________________
Gil F. |
|
|
|
FAQ 
Search
Register
Profile 
Log in to check your private messages 
Log in
