CCS C Software and Maintenance Offers
FAQFAQ   FAQForum Help   FAQOfficial CCS Support   SearchSearch  RegisterRegister 

ProfileProfile   Log in to check your private messagesLog in to check your private messages   Log inLog in 

CCS does not monitor this forum on a regular basis.

Please do not post bug reports on this forum. Send them to CCS Technical Support
use of WRERR bit

 
Post new topic   Reply to topic    CCS Forum Index -> General CCS C Discussion
View previous topic :: View next topic  
Author Message
Fabri



Joined: 22 Aug 2005
Posts: 275

View user's profile Send private message

use of WRERR bit
PostPosted: Tue Jan 28, 2014 1:40 am     Reply with quote
Hi to all,
I did some write eeprom test and try to understand use of WRERR.

This is my test:
I read and write same eeprom location every 1/2 second. At the same time, with automatic system, I switch off random power supply for some seconds. In this situation I found loss of data after some hours. After every wrote, as suggested some times ago, I read location doesn't used in firmware.

This is setup of PIC18F46K22
Quote:

#fuses HSM,NOPBADEN,NODEBUG,WDT,PROTECT,PUT,CPD,NOLVP,BROWNOUT,BORV19,NODEBUG,CPB,STVREN,NOPLLEN,NOFCMEN


At start-up, after lost of data, I read WRERR and it's set to 1.
After reset, in case of WRERR, can I know lost eeprom data and address ?

Thanks,
Fabri
Ttelmah



Joined: 11 Mar 2010
Posts: 19498

View user's profile Send private message

PostPosted: Tue Jan 28, 2014 2:14 am     Reply with quote
Address no,

All WRERR tell you is that a write operation was started, and did not properly complete. The data may have been written OK, or it may not. There is no record of the address involved.

Designing 'safe' write modes, is down to careful thought on your end.

Have two (or more) areas you use.
Have each packet written, include a 'packet count', and as it's last item, a checksum. Use a proper 16bit (or better) checksum.
Then the last packet, with a good checksum, is the 'last known good'.

Remember that WRERR will not set if (for instance) an EEPROM cell is failing, and does not write correctly. Worse, such a cell will if just written, often read back correctly, but will lose it's contents, after power is removed.
You need to checksum the data, and only accept it if the checksum reads back correctly.

WRERR, is a useful 'extra', to tell you that a write did not complete, but doesn't tell you any more than this.

Best Wishes
Fabri



Joined: 22 Aug 2005
Posts: 275

View user's profile Send private message

PostPosted: Tue Jan 28, 2014 2:50 am     Reply with quote
Ok,

I hope in way to recover eeprom data. I write one location at each time not more data in the same time, so I haven't checksum.
Really I haven't problem in production but I wan't to improve security of my system. I read some eeprom locations every one second and I write, in case of changes ram data into eeprom, every 10 seconds. There's any way to know state of power supply before read and write eeprom ?
In case I can decide to start or not write eeprom.

One another question is: In case of WRERR=1, and I read new eeprom loacation, does PIC can write into it ?

Thanks,
Fabri
RF_Developer



Joined: 07 Feb 2011
Posts: 839

View user's profile Send private message

PostPosted: Tue Jan 28, 2014 4:06 am     Reply with quote
Fabri wrote:
There's any way to know state of power supply before read and write eeprom ?
In case I can decide to start or not write eeprom.


You have to design the hardware so that a) the PIC can quickly detect when the power is failing AND b) make sure that once the power power is failing, there is enough left to make sure the PIC can write everything to EEPROM. It takes about 4ms per byte to write, and often you'll need to write several bytes, and the eeprom write is one of the functions in the PIC that needs the highest voltage (in other words its often the thing to fail first as the power goes down) so you need quite a long time of guaranteed power left after the power fail warning. A power fail warning is a good candidate for an interrupt, avoiding the delay typically caused by polling an I/O line.

An alternative is to stop writing something that you normally write frequently when you see the power fail indication. In other words doing a controlled shutdown.

You often can't add this hardware stuff in to existing designs: it needs to be done up front as part of a new design, or a significant upgrade to an old design.

Once the data is written wrongly, or even if the data is suspect, there's nothing that can be done: its too late, the data is corrupt.
Fabri



Joined: 22 Aug 2005
Posts: 275

View user's profile Send private message

PostPosted: Tue Jan 28, 2014 4:38 am     Reply with quote
Yes, you confirm me solution I already thought.

In my application I have zero crossing detect under interrupt. With this I can understand when AC power fall down and have time to stop write operation.
I have interrupt every 10ms so, In case I don't receve interrupt more than 20ms, I can stop write and have enough DC power supply to support operation.

What are you thinking about ?

Fabri
Display posts from previous:   
Post new topic   Reply to topic    CCS Forum Index -> General CCS C Discussion All times are GMT - 6 Hours
Page 1 of 1

 
Jump to:  
You cannot post new topics in this forum
You cannot reply to topics in this forum
You cannot edit your posts in this forum
You cannot delete your posts in this forum
You cannot vote in polls in this forum


Powered by phpBB © 2001, 2005 phpBB Group