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SPI 18f452 --> 18f4620

 
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micman2
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SPI 18f452 --> 18f4620
PostPosted: Wed Feb 21, 2007 4:26 am     Reply with quote
Hi,

I have a problem ,i'm working with SD/MMC SPI with the 18f452 works perfectly but when port the code on the pic 18f4620, the SD/MMC does not work correctly, because is some bug in the compiler?
teekaytk



Joined: 14 Jan 2005
Posts: 28

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PostPosted: Wed Feb 21, 2007 5:25 am     Reply with quote
there may be! i encountered similar problem. what compiler version are you using. i used 3.249 and the probelm was solved

regards
Guest
PostPosted: Wed Feb 21, 2007 8:08 am     Reply with quote
teekaytk wrote:
there may be! i encountered similar problem. what compiler version are you using. i used 3.249 and the probelm was solved

regards


Yes I read the post but I work with 4.020 Crying or Very sad
micman2
Guest
PostPosted: Wed Feb 21, 2007 8:08 am     Reply with quote
Anonymous wrote:
teekaytk wrote:
there may be! i encountered similar problem. what compiler version are you using. i used 3.249 and the probelm was solved

regards


Yes I read the post but I work with 4.020 Crying or Very sad


Yes I read the post but I work with 4.020
KaraMuraT



Joined: 16 May 2006
Posts: 65
Location: Ankara/Turkey

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It's because of the MSSP module
PostPosted: Wed Feb 21, 2007 9:19 am     Reply with quote
Hi,

This problem occurs because of the Erratas on the Nanowatt series PICs. (including 18F4620)

Read this PDF's caerfully and you'll see lots of silicon erratas.

http://ww1.microchip.com/downloads/en/DeviceDoc/80282a.pdf
http://ww1.microchip.com/downloads/en/DeviceDoc/80224c.pdf
http://ww1.microchip.com/downloads/en/DeviceDoc/80200d.pdf
http://ww1.microchip.com/downloads/en/DeviceDoc/80222b.pdf


For example, using I2C (MSSP module) in HW mode (FORCE_HW) causes lots of trouble. I just solved an issue regarding to this subject. and removed the "FORCE_HW" statement from #use i2c directive.

example errata from MSSP module:
Quote:

In SPI mode, the Buffer Full flag (BF bit in the SSPSTAT register), the Write Collision Detect bit (WCOL bit in SSPCON1) and the Receive
Overflow Indicator bit (SSPOV in SSPCON1) are not reset upon disabling the SPI module (by clearing the SSPEN bit in the SSPCON1 register).
For example, if SSPBUF is full (BF bit is set) and the MSSP module is disabled and re-enabled, the BF bit will remain set. In SPI Slave mode, a subsequent write to SSPBUF will result in a write collision. Also, if a new byte is received, a receive overflow will occur.

Work around

Ensure that if the buffer is full, SSPBUF is read (thus clearing the BF flag) and WCOL is clear before disabling the MSSP module. If the module
is configured in SPI Slave mode, ensure that the SSPOV bit is clear before disabling the module.

_________________
/// KMT
/// www.muratursavas.com
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